Analysis of Self Checking Additional Adder Circuit in Combinational Circuits
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 3
Abstract
Digital computers perform variety of information tasks; among the functions encountered are the various arithmetic operations. The most basic arithmetic operation is the addition and subtraction of two or more binary digits. In processors adders are used not only in the arithmetic logic units, but also in other parts of the processor, where they are used to calculate addresses, table indices and similar operations. The basic building block of many complex computational systems is the full adder. VLSI integrates a large system into a single chip. Self checking scheme is becoming an important design technique to full fill the requirements of modern computer systems with full reliability. The main aim of this paper is to provide the output of ripple carry adder without any error even when any one of the full adder is fault. The proposed system is built using VHDL, simulated using Xilinx ISE 12.1 and implemented using Spartan-3E FPGA and ALTERA Universal kit. This will fit the specified functional requirements and finds a solution to overcome the problem of fault in any one full adder.
Authors and Affiliations
Abirami S B, Manoj K, Maruthu Pandian C, Rajesh K
Keywords
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