CMOS VLSI ARCHITECTURE OF LOW POWER LEVEL SHIFTER
Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 0
Abstract
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. TINA tool has been used to show the existing and proposed results.
Authors and Affiliations
A. Vidhyalakshmi, S. Sobana
Keywords
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