Delay reduction for testing using LPFRSE
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2016, Vol 5, Issue 5
Abstract
Tracing the memory with a BIST approach is phenomenal, but verifying each bit in the memory and tracing the result is a high time consuming, high power utilizing and area constrained process. Here we are approaching for a speed and low power utilizing test using different test pattern generators using ATPG, scan and LP-LFSR. Comparing the area utilization, power utilization, time constrained and finally effective utilization of devices on the chips selected through simulations in Xilinx.
Authors and Affiliations
Md. Nadeem Qamar, Y. Arpitha , Dr. G. Chenchamma
Keywords
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