Design and Implementation of Wideband Digital Down Converter on FPGA
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 4
Abstract
In a Communication system, the received signals are of high data rates making it difficult to process the signals to extract information of interest. So to solve this problem DDC makes a better solution. In this paper, an efficient way of designing and implementing a Wideband Digital down Converter has been discussed. It is shown that the signal of interest extracted till now is of narrowband but in this article extraction of wideband signals from the given ADC signal using advanced filtering and decimation techniques has been presented. Filtering is implemented in stages to obtain efficient response. Multiplier-free filter implementation providing decimation rates fron 4 to 4096 has been implemented. Also, the reasons for choosing FPGA over ASSP’s to implement DDC are provided. Xilinx ISE 12.3 version software is used for simulating each block of DDC at system level testing and Chip Scope Pro Analyzer tool is used for board level testing. Vitex-5 FPGA with speed -2 is the hardware used for implementing the design.
Authors and Affiliations
K. S. Sushmitha , , G. Vimala Kumari
Keywords
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- EP ID EP104380
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