Design and Verification of Area Efficient High-Speed Carry Select Adder
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 6
Abstract
Design of area efficient and high-speed data path logic systems forms the largest areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is span for reducing the area in the CSLA. This work uses a simple and efficient gate-level modification to drastically reduce the area and power of the CSLA. Based on this modification 8, 16, 32, 64 and 128-bit square-root CSLA (SQRT CSLA) architectures have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area as compared with the regular SQRT CSLA. This work estimates the performance of the proposed designs in terms of delay, area are implemented in Xilinx ISE.
Authors and Affiliations
T. Ratna Mala, R Vinay Kumar, T Chandra Kala
Keywords
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