Area reduction in CSLA with efficient delay management Journal title: International Journal of Science Engineering and Advance Technology Authors: Ch Gayatri| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineer... Subject(s): Engineering, Medicine, Social Sciences, Pharmacy
Area Delay Power Efficient Carry Select Adder for Modern Signal Processors Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Chandrabose. J, M. Ravikumar Subject(s): Engineering, Applied Linguistics
Design and Verification of Area Efficient High-Speed Carry Select Adder Journal title: International Journal of Research in Computer and Communication Technology Authors: T. Ratna Mala, R Vinay Kumar, T Chandra Kala Subject(s): Computer and Information Science, Telecommunications
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Finding Logic Journal title: International Journal of engineering Research and Applications Authors: P.Pavani Sushma, J. Priyanka, R. Lalitha, K. Manoj, N. Divya Subject(s):
Implementation of Cmos Adder for Area & Energy Efficient Arithmetic Applications Journal title: American journal of Engineering Research Authors: Prachi B. Deotale1 ,, Umesh W. Kaware2 ,, Chetan G. Thote3 Subject(s):
