Design of Analog Integrated Circuits Based on Analysis of MOS Transistor Layout Effect

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Design of Analog Integrated Circuits Based on Analysis of MOS Transistor Layout Effect

Journal Title: 河南科技大学学报（自然科学版） - Year 2019, Vol 40, Issue 2

Abstract

To realize layout design automation for an analog integrated circuit ( IC) , the layout design methodology called metal-oxide-semiconductor field-effect transistor ( MOSFET) array was proposed in this paper. A 90 nm/1. 2 V complementary MOS testing elements group ( TEG) chip was manufactured for collecting the sampling data. The multi-finger gate MOS transistors based on various channel decompositions manner were implemented in this chip, and the transistors ware presented in different placement patterns in circuit layout design. The electrical parameters were measured and extracted, so the direct current ( DC) characteristics were analyzed and evaluated. Meanwhile, taking a two-stage operating amplifier as the design case, the transistor array layout and full-custom layout were employed for layout design. The performance analysis and comparison in terms of process variation and layout area were taken. The measurement results show that in case of the cascade operating amplifier with transistor array ( TA) style, the average value of offset voltages among 10 of TEG chips is 4. 48 m V. Compared to 5. 59 m V measured from custom layout, about 20% improvement of performance in aspect of process variation-tolerance is obtained, which shows the effectiveness of TA layout structure for analog circuits.

Authors and Affiliations

Bo LIU, Jincan ZHANG, Leiming ZHANG, Min LIU

Keywords

analog integrated circuit; layout effect; process variation; multi-finger MOS transistor;

EP ID EP422476
DOI 10.15926/j.cnki.issn1672-6871.2019.02.010
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