Design of CMOS Frequency Multiplier in 180nm Technology
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 6
Abstract
CMOS Frequency multipliers are key blocks in new developing applications at microwaves and mm-waves. Frequency multiplication is carried out in Radio Frequency or Microwave equipment to achieve high stability and low noise signals. Frequency multiplier circuits are utilized as a part of an extensive variety of applications in communication systems. In this paper, we have presented a method for designing a Digital Phase Locked Loop (DPLL) based Frequency Multiplier using Cadence Virtuoso 180nm CMOS Technology. The proposed circuit utilizes phase locked loop architecture to play out the frequency multiplication and is executed totally on-chip. Focal points of this topology incorporate excellent fundamental suppression, compact layout, and low power dissipation. The proposed design operates at the 3V power supply and provides less power dissipation of 1.46mW.
Authors and Affiliations
Anjali Sharma, Rekha Yadav
Keywords
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