Design of Pulse Triggered FlipFlop for Low Power Applications
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2015, Vol 5, Issue 1
Abstract
Most important challenge in modern VLSI design along with area and speed is the power consumption. Flip flop is the basic element in digital system which plays very important role. In this paper, a low power pulse triggered flip flop with feed through technique is proposed. The proposed design introduces a series pass transistor which helps in reducing discharging path. By performing post layout simulation of design based on 90nm technology using HSPICE at 500MHz/1.0V revel that the proposed design excels in performance indexes such as power, D-to-Q delay, EDP. Its maximum energy delay product saving is up to 49.77% compared with previous SCCER design.
Authors and Affiliations
Madge Deepali Harish| M.E. Student, E &TC Department, Vishwabharti Academy’s College of Engineering, Ahmednagar, Maharashtra, India, A. K. Kureshi| Vishwabharti Academy’s College of Engineering, Ahmednagar, Maharashtra, India
Keywords
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