Formation CMOS Schemes on GaAs with Self-Aligned Nitride and Silicide Gates

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Formation CMOS Schemes on GaAs with Self-Aligned Nitride and Silicide Gates

Journal Title: Фізика і хімія твердого тіла - Year 2015, Vol 16, Issue 2

Abstract

Advanced integrated logic circuits on GaAs are mainly based on the using of n-channel field-effect transistors with gate Schottky (MESFET). To create the complementary MESFET integrated circuits the main problem is quite small Schottky barrier height (< 0,5 eV) on p-type gallium arsenide. One way to solve this problem is to use a nitride or silicide tungsten compounds to form gates given the thickness and composition. This paper highlights the features of the formation of complementary high-speed logic circuits on the p-GaAs with self-aligned gate based on nitride or silicide of tungsten obtained by reduced pressure horizontal reactor "Izotron 4" and of RF magnetron sputtering equipment "Oratorio-5." This technology can also be used to form a Schottky contact to n- channel MESFET. Since the manufacturing process of MESFET self-aligned gate provides using refractory gate material as a mask for the multiply ion implantation, the Schottky contact must withstand subsequent high-temperature heat treatment required to activate implanted impurities. In this connection, the action of high-temperature photonic and resistive heating on the barrier height of Schottky contact formed by nitride (silicide) tungsten (WNx, WSix) GaAs was also studied.

Authors and Affiliations

S. P. Novosjadly, A. I. Terletsky, O. B. Fryk

Keywords

CMOS GaAs

EP ID EP308000
DOI 10.15330/pcss.16.2.420-424
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