High Speed Implementation Of Fused Floating Point Add-Subtract Unit
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2016, Vol 5, Issue 5
Abstract
Most universally useful processors (GPP) and application particular processors (ASP) utilize the coasting guide number-crunching due toward its wide and exact number framework. In any case, the coasting point operations require complex procedures, for example, arrangement, standardization and adjusting. To lessen the overhead, intertwined drifting point arithmetic units are introduced. High speed implementation of various fused-floating point add-subtract units are presented here. A fused floating-point add-subtract unit is proposed which has increased speed and reduced area compared to discrete floating- point adder. The proposed dual path add-subtract unit has increased performance than the fused floating-point addsubtract unit and this is achieved by employing a dual path algorithm. To further improve the speed, proposed architectures are implemented using six different adders and a comparative study is done. The fastest implementation is the dual path fused floating-point add-subtract unit using carry look ahead adder. The proposed designs are implemented for single precision and synthesized using Xilinx ISE 14.7.
Authors and Affiliations
Linsha L, Anoop E G, Benoy Abraham
Keywords
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