http://www.ijrcct.org/index.php/ojs/article/download/1385/pdf
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2016, Vol 5, Issue 5
Abstract
A performance efficient asynchronous parallel Self Timed Adder(PASTA) is presented in this paper. This adder achieves better performance even without any speedup circuitry/lookahed schem/carry skip unit. Skew problem are solved by Self-timing. The operation is done parallely for the bits that donot require carry chain propagation, this decreases the total delay. Recursive formula is used to perform multibit addition. The halfadders in the design makes it area efficient with minimal interconnection. The absence of clock generation and distribution units also results in less power dissipation. Clockless chips offer power efficiency, robustness and reliability. Digital simulation was done in Xilinx ISE 14.7 and implemented in Sparten 3E FPGA. Analog simulation was done in Tanner tool. An ALU was designed and synthesized using existing adder and proposed adder to show the superiority of the proposed approach.
Authors and Affiliations
Swathi V S, Sheelu Susan Mathews
Keywords
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