Implementation of Reconfigurable Router Architecture for NoC
Journal Title: International Journal for Modern Trends in Science and Technology - Year 2024, Vol 10, Issue 11
Abstract
Network on chip (NoC) becomes a promising solution for intercommunication infrastructure in System on Chip (SoC) as traditional methods exhibit severe bottlenecks at intercommunication among processor elements. However, designing of NoC is majorly complex because of lot of issues raise in terms of performance metrics such as system scalability, latency, power consumption and signal integrity. This paper discussed issues of memory unit in router and thereafter, proposing advanced memory structure. To obtain efficient data transfer, FIFO buffers are implemented in distributed RAM and virtual channels for FPGA based NoC. An advanced FIFO based memory units are proposed in NoC router and the performance is evaluated in Bi-directional NoC (Bi-NoC). The major motivation of this paper is to reduce burden of router while improving FIFO internal structure. To enhance the speed data transfer, Bi-NoC with a self-configurable intercommunication channel is proposed. The Simulations and synthesis results are proven guaranteed throughput, predictable latency, and fair network access highly provided when compared to recent works.
Authors and Affiliations
Akula Naga Sharath and Jyothula Sowjanya
Keywords
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- EP ID EP752208
- DOI https://doi.org/10.46501/IJMTST1011001
- Views 8
- Downloads 0
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