LabVIEW FPGA Based Noise Canceling Using the LMS Adaptive Algorithm
Journal Title: Acta Technica Napocensis- Electronica-Telecomunicatii (Electronics and Telecommunications) - Year 2009, Vol 50, Issue 4
Abstract
This paper proposes an architecture for implementing the Least Mean Square (LMS) adaptive algorithm, using a 20 bit fixed-point arithmetic representation. The architecture length was established to 16, but it can be easily modified. This is an advantage for large filter orders. The method can also be applied to other LMS versions. This architecture is implemented using the NI cRIO-9104 FPGA chassis. The NI cRIO-9012 is a real-time module used for signal control and storage. Experiments were done regarding signal to noise ratio (SNR), filter length and type of input signals. The obtained results indicate the implemented algorithm as having high performance, while still incurring some limitations. The design is evaluated in terms of SNR, filter length and FPGA resources.
Authors and Affiliations
Erwin SZOPOS, Horia HEDESIU
Keywords
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