Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Journal Title: International Journal of Electronics and Telecommunications - Year 2016, Vol 62, Issue 4
Abstract
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed
Authors and Affiliations
Raushan Kumar, Sahadev Roy, Chandan Tilak Bhunia
Keywords
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- EP ID EP200733
- DOI 10.1515/eletel-2016-0045
- Views 99
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