Low Power Single Phase Clock Multiband Flexible Divider Using Low Power Techniques
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2014, Vol 4, Issue 2
Abstract
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18µm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bitcell for swallow(S) counter and operates in 2.4 to 5 GHz resolution selectable from 1 to 25 MHz. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Low power Techniques like Sleep Transistor Approach and Dual Stack Sleepy P and Sleepy N.
Authors and Affiliations
Kishore Kumar Yelikipati| Kishore Kumar Yelikipati Electronics and Communication Engineering, Sasi Institute of Technology, Tadepalligudem, India, G Leenendra Chowdary| Assistant Professor, Department of Electronics and Communication Engineering, Sasi Institute of Technology, Tadepalligudem, India, C R S Hanuman| Associate Professor, Department of Electronics and Communication Engineering, Sasi Institute of Technology, Tadepalligudem, India
Keywords
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