Multi-Step Verification Environment for a Chip Design using SoC platform

Abstract

 This paper presented an efficient verification strategy for the platform based design. A goal of the verification task is to detect all design faults and provide with full verification coverage at the earlier design. The proposed verification strategy employed iterative verification stages. For a case study, this strategy was used in a verification of a modem chip design complying with IEEE 802.11a standard. It was successfully verified the entire design functionality and its interface with 100% coverage in shorter design cycles.

Authors and Affiliations

Je-Hoon Lee

Keywords

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  • EP ID EP138040
  • DOI -
  • Views 68
  • Downloads 0

How To Cite

Je-Hoon Lee (30).  Multi-Step Verification Environment for a Chip Design using SoC platform. International Journal of Engineering Sciences & Research Technology, 3(2), 727-731. https://europub.co.uk/articles/-A-138040