Performance Analysis of FINFET Based 16:4 Encoder and 4:16 Decoder-A Design Perspective
Journal Title: IOSR journal of VLSI and Signal Processing - Year 2018, Vol 8, Issue 6
Abstract
The growing technology for the silicon chip is becoming a demand day by day to ensure the optimization in area, power consumption and speed in the digital circuits. The CMOS technology is fast growing domain where the analog and digital circuits are designed and fabrication of IC's but still there is tradeoff in area i.e size of CMOS transistor, delay and power consumption. To optimize these parameters, the proposed research work incorporated the 32nm FinFET technology for designing of 16:4 encoder and 4:26 decoder. The comparative study has been done for silicon area, delay and power consumption and it is found that FinFET based encoder and decoder are produced better results. The 16:4 encoder occupied an area of 189.88um2, 4:16 decoder area is -170.04 um2 , power consumption of encoder and decoder are 2.68uW and 1.98uW and their delays are 24.4 microseconds, 19.56 microseconds. All simulation results and analysis are performed on 32um using Cadence Virtuoso software tool
Authors and Affiliations
1 Sujata. A. A, Dr. Lalitha. Y. S
Keywords
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