Performance Analysis of VLSI Circuits In 45nm Technology
Journal Title: International Journal of Engineering and Science Invention - Year 2018, Vol 7, Issue 5
Abstract
The optimization of power consumed in digital blocks of an Integrated Circuit while preserving the functionality is performed by Electronic Design Automation (EDA) tools. There is a significant increase in the power consumption of Very Large Scale Integration (VLSI) chips due to the increasing speed and complexity of today’s designs. Reduction of power is a great challenge. With today’s world of advancement in the IC technology there are over 100 million transistors, clocked at over 1 GHz which means manual power optimization would be very slow and a great certainty of errors, hence Cadence tools are necessary. Performance improved for 10T Full Adder,14T Full Adder and 28T Full Adder Circuit in terms of power and area reduced in 45nm technology Cadence SPECTRE simulator.
Authors and Affiliations
Sudhakar Alluri, N. Uma Umaheshwar, B. Rajendra Naik, N. S. S. Reddy
Keywords
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