Reduction and optimal performance of acyclic adders of binary codes
Journal Title: Восточно-Европейский журнал передовых технологий - Year 2019, Vol 1, Issue 4
Abstract
<p>The conducted studies have established the prospect of increasing productivity of computing components, in particular, combinational adders, based on applying principles of computation of digital signals of the acyclic model.</p><p>Application of the acyclic model is designed for:</p><p>‒ the process of series (for low-order digits of the adder circuit) and parallel (for the rest of the digits) computation of sum and carry signals. Due to this approach, it is possible, in the end, to reduce complexity of the hardware part of the device and not increase the circuit depth;</p><p>‒ setting the optimal number of computational steps.</p><p>The assumption that the number of computational steps of the directed acyclic graph with two logical operations (AND and XOR) determines optimal number of carry operations in the circuit of the n-bit parallel adder of binary codes was experimentally proved. In particular, this is confirmed by presence of the 8-bit parallel acyclic adder with the circuit depth of 8 standard 2-input logic elements. Connection between the number of computational steps of the acyclic graph and the number of operations of a unit carry to the high-order digit causes the process of comparison of the adder structure with the corresponding acyclic graph. The purpose of this comparison is to set the minimum sufficient number of carry operations for adding binary codes in the circuit of a parallel adder using the parallel carry method.</p><p>Use of the acyclic model is more advantageous in comparison with counterparts due to the following factors:</p><p>‒ less development costs since the acyclic model requires a simpler adder structure;</p><p>‒ presence of an optimization criterion, i.e. the number of computational steps of the acyclic graph indicates the minimum sufficient number of operations of a unit carry to the high-order digit.</p><p>This provides the possibility of obtaining optimum indicators of the adder structure complexity and circuit depth. Compared to counterparts of known 8-bit prefix adder structures, this provides a 14–31% increase in the 8-bit acyclic adder operation quality, e.g. power consumption or chip area depending on the chosen structure,</p>There are grounds to assert possibility of increasing productivity of computing components, in particular, binary code adders applying the principles of computation of digital signals of the acyclic model
Authors and Affiliations
Mykhailo Solomko, Petro Tadeyev, Yaroslav Zubyk, Olena Hladka
Keywords
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- EP ID EP666180
- DOI 10.15587/1729-4061.2019.157150
- Views 69
- Downloads 0
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