Safe Pre-Pass Software Bypassing for Transport Triggered Processors
Journal Title: Acta Technica Napocensis- Electronica-Telecomunicatii (Electronics and Telecommunications) - Year 2008, Vol 49, Issue 3
Abstract
The Transport Triggered Architecture is an architectural style where the internal transport buses of a processor are exposed in the instruction set. Since software has full control over data transports, data can be directly transfered between functional units, an optimization known as software bypassing. Software bypassing can potentially reduce the need for general purpose registers, because temporary values can be kept in functional units. Taking advantage of the reduced register pressure requires software bypassing to be done before register allocation and scheduling. In this paper we analyze under which conditions software bypassing can be done on a Data Dependence Graph without compromising the schedulability of the graph.
Authors and Affiliations
Pertti KELLOMAKI, Vladimir GUZMA, Jarmo TAKALA
Keywords
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