基于VHDL语言的数字锁相环的设计与实现
Journal Title: Science Paper Online - Year 2007, Vol 2, Issue 6
Abstract
为了改善数字通信系统的同步性能，保证系统工作稳定、可靠，本文对锁相环电路进行了研究，利用VHDL语言进行同步单元的全数字电路设计，并利用积分电路代替微分电路减小干扰；同时为了协调锁相环相位调节速度与抗干扰能力的矛盾，设计自动调节模块，使锁相环在具有很好的抗干扰能力的前提下，做到迅速地调节相位达到锁定状态；通过 MAX+plus II进行仿真，给出计算机仿真结果，验证设计的正确性。
Authors and Affiliations
Dong Yan
Keywords
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