VLSI Implementation of Fixed-Width Booth Multiplier Based on PEB Circuit
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2013, Vol 3, Issue 4
Abstract
This paper investigates methods of implementing binary multiplication with the smallest possible latency. A probabilistic estimation bias (PEB) circuit for a fixed-width two’s complement Booth multiplier is proposed for this investigation. The implementations developed for this study to indicate that traditional Booth encoded multipliers are superior in layout area, power, and delay to non-Booth encoded multiplier.
Authors and Affiliations
M. Mariya Shanthi| M. Tech (VLSI Design) Bharath University, Chennai, India, Dr. T. V. U. Kiran Kumar| Head, M. Tech, VLSI Design, Bharath University, Chennai, India
Keywords
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