A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes Journal title: The International Journal of Technological Exploration and Learning Authors: B.R.B Jaswanth| St.Theresa Institute of Engineering and Technology Gudiwada, India, R.V.S Rayudu| V.... Subject(s): Engineering, Educational Technology
Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement Journal title: International Journal of Research in Computer and Communication Technology Authors: A V S Swathi, M Lakshmi Prasanna Rani Subject(s): Computer and Information Science, Telecommunications
PERFORMANCE EVALUATION OF AN EFFICIENT SINGLE EDGE TRIGGERED D FLIP FLOP BASED SHIFT REGISTERS USING CNTFET Journal title: Indian Journal of Computer Science and Engineering Authors: Ravi.T , Kannan.V Subject(s):
Design of Power Efficient Double Edge Triggered DLL Clock Generator Journal title: International journal of Emerging Trends in Science and Technology Authors: V. Yamuna Subject(s):
A Low Power Memory Architecture for Zigbee Trans-Receiver Journal title: GRD Journal for Engineering Authors: M. Marudhupandian, V. Kamalkumar Subject(s):
LOW POWER AND ENERGY EFFICIENT FLIP-FLOPS USING FLOATING GATE AND QUASI FLOATING GATE TECHNIQUES AT 180NM Journal title: Indian Journal of Scientific Research Authors: SWETA KUMARI Subject(s):
