Reversible Multiplier with Peres Gate and Full Adder Journal title: International Journal of Electronics Communication and Computer Technology Authors: Prof. Amol D. Morankar| Dept. of Electronics and Telecommunication Engg. V.N.I.T Nagpur, India, Prof... Subject(s): Computer and Information Science, Engineering
Memory Design Using Logical Gates Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Mandisha Sharma , Mansi Kakkar, Manish Sharma Subject(s): Engineering, Applied Linguistics
High Speed Design of an Information Lossless 8 Bit Carry Select Adder using CNT FET Journal title: International Journal of Research in Computer and Communication Technology Authors: S.Manisha Sree Adithtya, S.P.Saraswathi, S.Niranjana Subject(s): Computer and Information Science, Telecommunications
Design of Reversible Counter Journal title: International Journal of Advanced Computer Science & Applications Authors: Md. Selim Mamun, B. K. Karmaker Subject(s):
Quantum Cost Optimization for Reversible Sequential Circuit Journal title: International Journal of Advanced Computer Science & Applications Authors: Md. Selim Mamun, David Menville Subject(s):
An Area Efficient and High Speed Reversible Multiplier Using NS Gate Journal title: International Journal of engineering Research and Applications Authors: Venkateswarlu Mukku, Jaddu Mallikharjuna Reddy Subject(s):
