A COMPARATIVE STUDY OF DIFFERENT TYPES OF MIXER TOPOLOGIES
Journal Title: ICTACT Journal on Microelectronics - Year 2016, Vol 2, Issue 1
Abstract
In this paper, a comparative study of different types of mixer topologies is presented. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. A very low value of noise figure can be achieved with the switched biasing technique by replacing current source with parallel connected nMOS transistors but due to use of the transistor in place of tail current source, linearity is degraded and more power is consumed. Folded Cascode Technique is used to reduce DC supply voltage by folding the LO switching stage with pMOS transistors in switching stage but it degrades the noise figure. Bulk-driven technique can be employed to lower down the power consumption by providing the switching action via the gate of LO (RF) and amplification by the bulk of LO (RF) transistors, however it reduces the linearity. High linearity is obtained by using CCPD (Cross coupled post distortion) technique by cancelling of third order derivatives but it decreases the conversion gain and consume more power due to increase in the number of auxiliary transistors. MGTR enables to achieve high linearity by incorporating auxiliary transistor but it decreases the overall conversion gain and increases noise figure of the mixer. So it is observed that there is a trade-off among the performance metrics, i.e., conversion gain, noise figure linearity, and power consumption of the mixer.
Authors and Affiliations
Rahul Sharma, Abhay Chaturvedi, Manish Kumar
Keywords
Related Articles
- EP ID EP198126
- DOI 10.21917/ijme.2016.0031
- Views 133
- Downloads 0
LOW POWER AND HIGH PERFORMANCE SHIFT REGISTERS USING PULSED LATCH TECHNIQUE
This work presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. Pulsed-latch technique retain the advantages of both latches and flip-flops and thus one can a...
A NOVEL FINFET BASED APPROACH FOR THE REALIZATION OF TERNARY GATES
The Scaling of conventional Complementary Metal Oxide Semiconductors (CMOSs) has been facing problems such as short channel effect due to hot electron effect and leakage power. Fin Field Effect Transistor (FinFET) is con...
FPGA BASED STANDALONE EMBEDDED WEB SERVER FOR REMOTE CONTROL OF DISPLAY DEVICES
The Field Programmable Gate Array (FPGA) devices are quickly replacing the microcontrollers for embedded applications since they offer both the performance of hardware and flexibility of software computing. Custom logic...
PERFORMANCE ANALYSIS OF ADIABATIC TECHNIQUES USING FULL ADDER FOR EFFICIENT POWER DISSIPATION
Adiabatic circuits are low power circuits, which deals with reversible logic that it stores the power and gives it back again. Currently Several Adiabatic techniques have been adopted for efficient power dissipation. The...
VLSI IMPLEMENTATION OF HIGH SPEED AREA EFFICIENT ARITHMETIC UNIT USING VEDIC MATHEMATICS
High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multi-functions and have multiplier as the critical element. In this paper, we present desi...