A Cost Effective Design of Reversible Single Precision Floating Point Multiplier
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 1
Abstract
The emerging computing technologies like quantum computing, optical computing, low power computing etc. make use of reversible logic. Also applications like image processing and signal processing make use of floating point (FP) multiplications as the major operations. In this paper we propose the design of a low power, cost effective reversible floating point multiplier for such applications. The proposed design is comparable with the reversible FP multipliers discussed in the literature so far. The proposed design using TSG gates is cost effective in terms of the number of quantum gates and the garbage outputs compared to the existing ones. Since it has been proved that the ‘4 x 4’ TSG gate [4] can work singly as a reversible full adder with only two garbage outputs, it is an optimal reversible full adder with universal functionalities. Hence the proposed design yields an optimal floating point multiplier in terms of quantum cost and garbage outputs. The proposed design has three stages - partial product generation, compression using 4:2 TSG compressors and the final stage which consists of TSG adders to generate the resultant product. The proposed design of 32 x 32 bit FP multiplier is illustrated using TSG gates which show that the number of garbage outputs in each 8X8 multiplier is reduced significantly.
Authors and Affiliations
Malathi S. R, Akshaya Venugopal, Pavithra Sarathy
Keywords
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