Design of Parallel Analog to Digital Converter Based on Darlington CMOS Inverter

Abstract

This article presents a 4-bit parallel analog-to-digital converter was designed by using Darlington CMOS Inverter which is operated in accordance with CMOS threshold voltage. Thus, there is no need to use resistance array block for obtaining quantization voltage in this structure. Generally, the darlington structure is used on bipolar junction transistor circuits, however it is proposed for CMOS circuits in this study. Hence, the gain of inverter circuit increases. According to simulation results, power consumption is 96.6mW, DNL and INL errors are (-0.71/+0.82)LSB and (0/-1.24)LSB respectively. The provided power consumption, DNL and INL measures are observed at 100MHz input with 10GS/s sampling rate. All the simulation results were obtained from schematic circuits.

Authors and Affiliations

Oktay AYTAR

Keywords

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  • EP ID EP489627
  • DOI 10.29109/http-gujsc-gazi-edu-tr.358045
  • Views 104
  • Downloads 0

How To Cite

Oktay AYTAR (2018). Design of Parallel Analog to Digital Converter Based on Darlington CMOS Inverter. Gazi Üniversitesi Fen Bilimleri Dergisi Part C: Tasarım ve Teknoloji, 6(1), 67-78. https://europub.co.uk/articles/-A-489627