FPGA Bit-stream Compression Using Run-length Encoding
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2013, Vol 3, Issue 2
Abstract
Reconfigurable system uses bit-stream compression to reduce the bit-stream size and the memory requirement. The communication bandwidth is improved reducing the reconfiguration time. Existing research has explored efficient compression with slow decompression or fast decompression at the cost of compression efficiency. This paper proposes a decode-aware compression technique to improve both compression and decompression efficiencies. The three major contributions of this paper are: i) Efficient bitmask selection technique that can create a large set of matching patterns; ii) Proposes a bitmask based compression using the bitmask and dictionary selection technique that can significantly reduce the memory requirement iii) Efficient combination of bitmask-based compression and run length encoding of repetitive patterns.
Authors and Affiliations
P. M. Sandeep| P.G. Scholar ,M.E.VLSI Design Sri Ramakrishna Engineering College Coimbatore, India, C. S Manikandababu| Assistant Professor, M.E. VLSI Design Sri Ramakrishna Engineering College Coimbatore, India
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