Power Optimization In Digital Circuits Using Scan-Based BIST
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 6
Abstract
Technology provides smaller, faster and lower energy devices which allow more powerful and compact circuit- ry. Thermal and shot-noise estimations alone suggest that the fault rate of an individual Nano scale device may be orders of magnitude higher than today’s devices. For that purpose, going for Built in self-test (BIST). BIST-test patterns are generated and applied to the cir- cuitunder-test (CUT) by on-chip hardware and minimizing hardware overhead is a major concern of BIST implementation. This Paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST). The proposed BS-LFSR for test-per-scan BISTs is based upon some new observations concerning the num- ber of transitions produced at the output of an LFSR. The average and peak power is reduced while capturing the vectors by using scan chain reordering. BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power in the test cycle or while scanning out a re- sponse to a signature analyzer. The problem of the cap- ture power will be solved by using a novel algorithm that will reorder some cells in the scan chain in such a way that minimizes the Hamming distance between the ap- plied test vector and the captured response in the test cycle. This technique of reducing power consumption significantly increases the test application time.
Authors and Affiliations
Ramakrishna Porandla, Gella Ravikanth, Podili Ramu
Keywords
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