Area reduction in CSLA with efficient delay management Journal title: International Journal of Science Engineering and Advance Technology Authors: Ch Gayatri| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineer... Subject(s): Engineering, Medicine, Social Sciences, Pharmacy
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Finding Logic Journal title: International Journal of engineering Research and Applications Authors: P.Pavani Sushma, J. Priyanka, R. Lalitha, K. Manoj, N. Divya Subject(s):
Implementation of Cmos Adder for Area & Energy Efficient Arithmetic Applications Journal title: American journal of Engineering Research Authors: Prachi B. Deotale1 ,, Umesh W. Kaware2 ,, Chetan G. Thote3 Subject(s):
An Area and Speed Efficient Square Root Carry Select Adder Using Optimized Logic Units Journal title: International Journal of Innovative Research in Computer Science and Technology Authors: Dr.P.Bhaskara Reddy, S.V.S. Prasad, K. Ananda Kumar Subject(s): Electrical and Electronic Engineering, Chemical Engineering, Civil Engineering, Computer Science, Artificial Intelligence, Computer Science, Information Systems, Computer Science, Interdisciplinary Applications, Engineering, Multidisciplinary, Engineering, Civil, Computer Science, Cybernetics, Computer Science, Theory & Methods, Computer Science, Software Engineering
