Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 4
Abstract
FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This Processor Architecture is based on parallel processing in which more than one instruction is executed in parallel. This architecture is used to increase the instruction throughput. So this is the base of the modern Superscalar Processors. Basically VLIW is a RISC Processor. The difference is it contains long instruction as compared to RISC. This stage of the pipeline executes the instruction. This is the stage where the ALU (arithmetic logic unit) is located. Execute stage are synthesized and targeted for Xilinx Virtex 4 FPGA and the results calculated for 64-bit Execute stage improve the power as compared to previous work done.
Authors and Affiliations
Manju Rani| ECED, Thapar University Patiala, Patiala, India, Harpreet Vohra| ECED, Thapar University Patiala, Patiala, India
Keywords
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