FPGA Based Implementation of Genetic Algorithm Using VHDL
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2011, Vol 1, Issue 1
Abstract
The research on genetic algorithm is normally concentrate on software Implementation, which is always restricted in term of high real time by computer system because it is serial calculation. This paper introduces a hardware structure on FPGA based genetic algorithm which programmed by VHDL language .Simulation is performed by Xilinx 8.1i and modelsim and implement on FPGA spartan3.
Authors and Affiliations
Vikas Gupta| Electronics &Communication T.I.T Bhopal, India vgup24@yahoo.com, Anshuj Jain| Electronics &Communication T.I.T Bhopal, India anshuj2008@gmail.com, Bharti Chourasia| Electronics &Communication SCOPE College, Bhopal, India bharti.chourasia@gmail.com
Comparative Study of 4G Technology, Applications and Compatibility in Prevailing Networks
With increasing end user demands for wider service due to the rapid growth and variety of IT (information technology) industry, the service with the data rate of 30 Mbps cannot accommodate the future mobile multimedia en...
Practical Implementation and Performance Analysis of Improved-DSR Protocol using ZigBee in Wireless Sensor Network
Wireless sensor networks are self-configuring network of mobile and static nodes connected by wireless link. The communication in WSN is uncertain because established route can be broken anytime. A lot of delay occurs...
Construction Of 3phase Sine Waves Using Digital Technique
Abstract—All the real world parameters such as temperature, pressure etc., are analog in nature, In order to control these physical parameters using computers, which are digital in nature, high speed signal processing bo...
Reversible Multiplier with Peres Gate and Full Adder
Low Power dissipation and smaller area are one of the important factors while designing multipliers for digital circuits. As multipliers used in digital circuits dissipate large amount of heat whenever there is a tran...
A Novel Low Power Topology in Reversed Nested Miller Compensation Using Triple-Active Capacitance
A novel three-stage amplifier topology for low voltage , low power and large capacitive load applications is proposed . This scheme is called the tripple-active capacitance and resistance in reversed nested Miller compen...