Reduced Area and Improve Delay Module Design of 64 × 16 RAM
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2014, Vol 4, Issue 4
Abstract
This paper describes a new design approach of RAM in which word can be accessed by row decoder & column decoder, which give the concept of 2-Dimentional RAM. The 64 × 16 RAM has 16-bit data length. This can read and write 16-bit data. All the module of the design are coded in VHDL with the concept of concurrency. The behavioral and structural representation of this design has been defined. Objective of this paper are focused on design of 2-Dimensional RAM using active HDL & evaluate simulation result.
Authors and Affiliations
Raj Kumar Mistri| Department of Electronics & Communication Engineering, RTCIT, Ranchi, Jharkhand, India, Poonam Soley| Department of Electronics & Communication Engineering, RTCIT, Ranchi, Jharkhand, India, Prakash Mahto| Department of Electronics & Communication Engineering, RTCIT, Ranchi, Jharkhand, India, Nitu Kumari| Department of Electronics & Communication Engineering, RTCIT, Ranchi, Jharkhand, India, Pramod Kumar Thakur| Department of Electronics & Communication Engineering, RTCIT, Ranchi, Jharkhand, India
Keywords
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