Implementation of Different Low Power Multipliers Using Verilog Journal title: The International Journal of Technological Exploration and Learning Authors: Koteswara Rao Ponnuru| M. Tech, Assistant Professor SRK Institute of Technology Vijayawada, A.P., In... Subject(s): Engineering, Educational Technology
Switching Activity Reduction Technique In Soc Testing Journal title: International Journal of Science Engineering and Advance Technology Authors: P. Sai Kumar| M.Tech Scholor Vlsi Design, N. S. Govind| Asst. Professor H.O.D (E.C.E) Subject(s): Engineering, Medicine, Social Sciences, Pharmacy
Implementation of Dadda and Array Multiplier Architectures Using Tanner Tool Journal title: International Journal of Computer Science & Engineering Technology Authors: Addanki Purna Ramesh Subject(s):
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Using Reversible Adder Journal title: International Journal of Modern Engineering Research (IJMER) Authors: V S Chunduri, G. Lakshmi, Dr.M. Prasad Subject(s):
Design and implementation of 4-bit Vedic Multiplier Journal title: International journal of Emerging Trends in Science and Technology Authors: Anannya Maiti Subject(s):
An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic Journal title: Elektronika Authors: Shoba Mohan, Nakkeeran Rangaswamy Subject(s):
Timing Analysis of Generic Multipliers Journal title: IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) Authors: Anju Rajput Subject(s):
The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications Journal title: Annals of Emerging Technologies in Computing Authors: Mohsen Sadeghi, Mahya Zahedi, Maaruf Ali Subject(s):
