High-Rapidity and Power-Efficient Carry Skip Adder Performance with AOI and OAI Skip Logic Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: AmrutaVarshini S H, Mr. S Pramod Kumar Subject(s): Engineering, Applied Linguistics
Implementation And Analogy Of Fast Adder Using Fpga Journal title: International Journal of Research in Computer and Communication Technology Authors: Preeti S.Manohare, Rohit C. Iyer Subject(s): Computer and Information Science, Telecommunications
A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Mrudula Singamsetti , Sarada Musala Subject(s):
32 Bit Parallel Multiplier Using VHDL Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey Subject(s):
Self-timed Circuit Device Size Optimization for an Input Data Distribution Journal title: International Journal of Computer Science & Engineering Technology Authors: Alvernon Walker , Evelyn R. Sowells Subject(s):
An Improved Optimization Techniques for Parallel Prefix Adder using FPGA Journal title: International Journal of Modern Engineering Research (IJMER) Authors: O. Anjaneyulu, L. Swapna, C.V. Reddy Subject(s):
Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow Journal title: International Journal of Advanced Computer Science & Applications Authors: Abdul Buzdar, Liguo Sun, Abdullah Buzdar Subject(s):
Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Gagandeep Singh , Chakshu Goel Subject(s):
[b][i]Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique[/i][/b] Journal title: International Journal of Modern Engineering Research (IJMER) Authors: Nitin Singh , M. Zahid Alam Subject(s):
High Speed and Reduced Power – Radix-2 Booth Multiplier Journal title: International Journal of Computational Engineering and Management IJCEM Authors: Sakshi Rajput, Priya Sharma, Gitanjali, Garima Subject(s):
Comparative Analysis of Adders Journal title: International Journal of Science and Research (IJSR) Authors: Subject(s):
Design of Low Power Vedic Multiplier Based on Reversible Logic Journal title: International Journal of engineering Research and Applications Authors: Sagar ., K Suresh Babu Subject(s):
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Finding Logic Journal title: International Journal of engineering Research and Applications Authors: P.Pavani Sushma, J. Priyanka, R. Lalitha, K. Manoj, N. Divya Subject(s):
DESIGN OF LOW POWER 32-BIT CSKA FOR HIGH SPEED APPLICATIONS Journal title: Elysium Journal of Engineering Research and Management Authors: Yamini C., Krishnamurthy M Subject(s):
VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TECHNOLOGIES AND MANAGEMENT RESEARCH Authors: Subject(s):
