Design of Improved Array Multiplier by Carry Select Logic Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Silpa Raj P, Punitha V Subject(s): Engineering, Applied Linguistics
Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Nalina R, Ashwini S S, Dr. M Z Kurian Subject(s): Engineering, Applied Linguistics
Implementation of Optimized 64 Bit MAC using Vedic Multiplier and Reverse Logic Gate Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Savitha S, S. Raja, Amrutha Soroobini S, Anusruthi K, Barani Priya L Subject(s): Engineering, Applied Linguistics
Design of Modulo 2n-1 based on Radix-8 Algorithm for RNS & MAC Applications Journal title: International Journal of Research in Computer and Communication Technology Authors: Neredimelli V V P Hide, Dr. I. Santi Prabha Subject(s): Computer and Information Science, Telecommunications
Design and Verification of Area Efficient High-Speed Carry Select Adder Journal title: International Journal of Research in Computer and Communication Technology Authors: T. Ratna Mala, R Vinay Kumar, T Chandra Kala Subject(s): Computer and Information Science, Telecommunications
Implementation And Analogy Of Fast Adder Using Fpga Journal title: International Journal of Research in Computer and Communication Technology Authors: Preeti S.Manohare, Rohit C. Iyer Subject(s): Computer and Information Science, Telecommunications
Design and Implementation of FPGA Radix-4 Booth Multiplication Algorithm Journal title: International Journal of Research in Computer and Communication Technology Authors: A.Rama Vasantha, M.Sai Satya Sri Subject(s): Computer and Information Science, Telecommunications
Self-Checking Carry-Select Adder Design Based on Two-Pair Two-Rail Checker Journal title: International Journal of Research in Computer and Communication Technology Authors: P.S.D. Lakshmi, K. Srinivas, R.Satish Kumar Subject(s): Computer and Information Science, Telecommunications
An Area-Efficient Carry Select Adder Design by using 180 nm Technology Journal title: International Journal of Advanced Computer Science & Applications Authors: Garish Kumar Wadhwa , Amit Grover , Neeti Grover , Gurpreet Singh Subject(s):
Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Gagandeep Singh , Chakshu Goel Subject(s):
Design and Comparative Analysis of CMOS Full Adder Cells Using Tanner EDA Tool Journal title: International Journal of Computer Science & Engineering Technology Authors: JATINDER KUMAR Subject(s):
High Speed and Reduced Power – Radix-2 Booth Multiplier Journal title: International Journal of Computational Engineering and Management IJCEM Authors: Sakshi Rajput, Priya Sharma, Gitanjali, Garima Subject(s):
Comparative Analysis of Adders Journal title: International Journal of Science and Research (IJSR) Authors: Subject(s):
An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic Journal title: Elektronika Authors: Shoba Mohan, Nakkeeran Rangaswamy Subject(s):
High Speed Low Power Radix-4 Modified Booth Novel Carry Select Adder Based Multiplier and Multiply Accumulate (MAC) Unit Journal title: Scholars Journal of Engineering and Technology Authors: Mala Sinnoor Subject(s):